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7-bit,programmable,dual- phase,mobile,cpu,synchronous buck controller preliminary ADP3208C may 2008C rev. 1 features single-chip solution fully compatible with the inte l? imvp-6+? specifications integrated mosfet drivers input voltage range of 3.3 v to 22 v selectable 1- or 2-phase operation with up to 1 mhz per phase switching frequency guaranteed 8 mv worst-case differentially sensed core voltage error over temperature automatic power-saving mode maximizes efficiency with light load during deeper sleep operation soft transient control reduces inrush current and audio noise active current balancing between output phases independent current limit and load line setting inputs for additional design flexibility built-in power-good blanking supports voltage identification (vid) on-the-fly transients 7-bit, digitally programmable dac with 0.3 v to 1.5 v output short-circuit protection with latch-off delay clock enable output delays the cpu clock until the core voltage is stable output load current monitor 48-lead lfcsp applications notebook power supplies for next-generation intel processors general description the ADP3208C is a highly efficient, multiphase, synchronous buck switching regulator controller. with its integrated drivers, the ADP3208C is optimized for converting the notebook battery voltage into the core supply voltage required by high performance intel processors. an internal 7-bit dac is used to read a vid code directly from the processor and to set the cpu core voltage to a value within the range of 0.3 v to 1.5 v. the phase relationship of the output signals ensures interleaved 2- phase operation. the ADP3208C uses a multimode architecture run at a programmable switching frequency and optimized for efficiency depending on the output current requirement. the ADP3208C switches between single- and dual-phase operation to maximize efficiency with all load conditions. the chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. the ADP3208C also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power-good output. the ic supports on-the-fly output voltage changes requested by the cpu. the ADP3208C is specified over the extended commercial temperature range of -10c to 100c and is available in a 48-lead lfcsp.
ADP3208C rev. 1 | page 2 of 41 | www.onsemi.com functional block diagram + - vid dac vid6 vid5 vid4 vid3 vid2 vid1 vid0 fbrtn clken start up delay clken start up delay clken open drain clken open drain pwrgd start up delay clken pwrgd pwrgd open drain + - + - csref dac - 300mv soft transient delay delay disable dac - + - + csref cssum cscomp ilimn thermal throttle control thermal throttle control ttsns vrtt + - + - ovp csref 1.7v + - + - _ + lline ref ref + + vea fb comp uvlo shutdown and bias uvlo shutdown and bias vcc en gnd rpm rt ramp current balancing circuit current balancing circuit imon dprslp dprslp logic iref psi psi current monitor bst1 drvh1 current limit circuit ocp shutdown delay sw1 pgnd1 drvl1 pvcc1 bst2 drvh2 sw2 drvl2 pgnd2 driver logic precision reference precision reference soft start soft transient varfreq pvcc2 dac - 200mv ilimp dprstp dprstp dprstp dprstp oscillator sp figure 1.
ADP3208C rev. 1 | page 3 of 41 | www.onsemi.com table of contents features...............................................................................................1 applications .......................................................................................1 general description..........................................................................1 functional block diagram ...............................................................2 revision history................................................................................3 specifications .....................................................................................4 timing diagram................................................................................9 absolute maximum ratings ..........................................................10 esd caution ................................................................................10 pin configuration and function descriptions ...........................11 test circuits .....................................................................................13 typical performance characteristics............................................15 theory of operation .......................................................................19 number of phases .......................................................................19 operation modes ........................................................................19 differential sensing of output voltage ....................................22 output current sensing .............................................................22 active impedance control mode..............................................22 current control mode and thermal balance ....23 voltage control mode ................................................................23 power-good monitoring............................................................23 power-up sequence and soft start ...........................................23 soft transient...............................................................................24 current limit...............................................................................24 changing vid on the fly...........................................................25 output crowbar ...............................................................26 reverse voltage protection ........................................................27 output enable and uvlo.........................................................27 thermal throttling control ......................................................27 current monitor function ......................................27 application information ................................................................31 setting the clock frequency for pwm....................................31 setting the switching frequency for rpm operation of phase 1 .....................................................................................................31 inductor selection.......................................................................31 c out selection..............................................................................33 power mosfets .........................................................................34 ramp resistor selection.............................................................35 comp pin ramp ........................................................................35 current limit setpoint...............................................................36 output current monitor ............................................................36 feedback loop compensation design ....................................36 c in selection and input current di/dt reduction ..................37 selecting thermal monitor components................................38 tuning procedure for ADP3208C ............................................38 layout and component placement ..........................................39 outline dimension .........................................................................41 ordering guide ...........................................................................41 revision history 5/08- rev 1: initial preliminary version
ADP3208C rev. 1 | page 4 of 41 | www.onsemi.com specifications vcc = pvcc1 = pvcc2 = bst1 = bst2 = high = 5 v, fbrtn = gn d = sw1 = sw2 = pgnd1 = pgnd2 = low = 0 v, en = varfreq = high, dprslp = 0 v, psi = 1.05 v, v vid = 1.2000 v, t a = -10c to 100c, unless otherwise noted. 1 current entering a pin (sunk by the device) has a positive sign. r ref = 80 k . table 1. parameter symbol conditions min typ max units voltage control voltage error amplifier (veamp) fb, lline voltage range 2 v fb , v lline relative to csref = vdac ?200 +200 mv fb, lline offset voltage 2 v osvea relative to csref = vdac -0.5 +0.5 mv fb, lline bias current 2 i fb ?100 100 na lline positioning accuracy v fb ? v vid measured on fb relative to v vid , lline forced 80 mv below csref ?78 ?80 ?82 mv comp voltage range 2 v comp operating range 0.85 4.0 v comp current i comp comp = 2 v, csref = vdac fb forced 200 mv below csref fb forced 200 mv above csref ?0.75 6 ma ma comp slew rate sr comp c comp = 10 pf, csref = vdac, open loop configuration fb forced 200 mv below csref fb forced 200 mv above csref 15 ?20 v/ s v/ s gain bandwidth 2 gbw non-inverting unit gain configuration, r fb = 1 k 20 mhz vid dac voltage reference vdac voltage range 3 see vid table 0 1.5 v vdac accuracy v fb ? v vid measured on fb (includes offset), relative to v vid , for vid table see table 6 v vid = 1.2125v to 1.5000v v vid = 0.3000v to 1.2000v ?9 ?7.5 +9 +7.5 mv mv vdac differential nonlinearity 2 ?1 +1 lsb vdac line regulation v fb vcc = 4.75 v to 5.25 v 0.05 % vdac boot voltage 2 v bootfb measured during boot delay period 1.200 v soft-start delay 2 t dss measured from en pos edge to fb = 50 mv 200 s soft-start time t ss measured from en pos edge to fb settles to vboot = 1.2 v within -5 % 1.7 ms boot delay t boot measured from fb settling to vboot = 1.2 v within -5 % to clken# neg edge 150 s vdac slew rate soft-start non-lsb vid step, dprslp = h, slow c4 entry/exit non-lsb vid step, dprslp = l, fast c4 exit 0.0625 0.25 1 lsb/ s lsb/ s lsb/ s fbrtn current i fbrtn 90 200 a voltage monitoring and protection power good csref under-voltage threshold v uvcsref relative to dac voltage = 0.5 v to 1.5 v relative to dac voltage = 0.3 v to 0.4875 v ?360 ?360 ?300 ?200 ?240 ?160 mv mv csref over-voltage threshold v ovcsref relative to nominal dac voltage 150 200 250 mv
ADP3208C rev. 1 | page 5 of 41 | www.onsemi.com parameter symbol conditions min typ max units csref crowbar voltage threshold v cbcsref relative to fbrtn 1.57 1.7 1.78 v csref reverse voltage threshold v rvcsref relative to fbrtn, latch-off mode csref falling csref rising ?350 ?300 ?70 ?5 mv mv pwrgd low voltage v pwrgd i pwrgd(sink) = 4 ma 50 150 mv pwrgd high, leakage current i pwrgd v pwrdg = 5 v 0.1 a pwrgd start-up delay t sspwrgd measured from clken neg edge to pwrgd pos edge 8 ms pwrgd latch-off delay t loffpwrgd measured from out-off-good-window event to latch-off (switching stops) 8 ms pwrgd propagation delay 3 t pdpwrgd measured from out-off-good-window event to pwrgd neg edge 200 ns crowbar latch-off delay 2 t loffcb measured from crowbar event to latch-off (switching stops) 200 ns pwrgd masking time triggered by any vid change or ocp event 100 s csref soft-stop resistance en = l or latch-off condition 70 current control current-sense amplifier (csamp) cssum, csref common- mode range 2 voltage range of interest 0 2 v cssum, csref offset voltage v oscsa csref C cssum t a = C10 c to 85 c t a = 25 c ?1.7 ?0.5 +1.7 +0.5 mv mv cssum bias current i bcssum ?50 +50 na csref bias current i bcsre ?120 +120 na cscomp voltage range 2 operating range 0.05 2 v cscomp current i cscompsource i cscompsink cscomp = 2 v cssum forced 200 mv below csref cssum forced 200 mv above csref ?750 1 a ma cscomp slew rate c cscomp = 10 pf, open loop configuration cssum forced 200 mv below csref cssum forced 200 mv above csref 10 ?10 v/ s v/ s gain bandwidth 2 gbw csa non-inverting unit gain configuration r fb = 1 kohm 20 mhz current monitoring and protection current reference iref voltage v ref r ref = 80 k to set i ref = 20 ua 1.55 1.6 1.65 v current limiter (ocp) current limit (ocp) threshold v limth measured from cscomp to csref, r lim = 4.5 k, 2-ph configuration, psi = h 2-ph configuration, psi = l ?70 ?32 ?95 ?47.5 ?115 ?65 mv mv 1-ph configuration ?70 ?95 ?115 mv current limit latch-off delay measured from ocp event to pwrgd de-assertion 8 ms current monitor current gain accuracy i mon /i lim measured from ilimp to imon i lim = ?20 a i lim = ?10 a i lim = ?5 a 9.5 9.4 9 10 10 10 10.5 10.7 11 - - - imon clamp voltage v maxmon relative to fbrtn, ilimp = -30 ua 1.0 1.15 v
ADP3208C rev. 1 | page 6 of 41 | www.onsemi.com parameter symbol conditions min typ max units pulse width modulator clock oscillator rt voltage v rt varfreq = high, r t = 125 k , v vid = 1.5000 v varfreq = low see also v rt (v vid ) formula 1.22 0.98 1.25 1 1.27 1.02 v v pwm clock frequency range 2 f clk operating range 0.3 3 mhz pwm clock frequency f clk t a = +25c, v vid = 1.2000 v r t = 73 k r t = 125 k r t = 180 k 970 705 500 1270 830 600 1570 955 700 khz khz khz ramp generator ramp voltage v ramp en = high, i ramp = 30 a en = low 0.9 1 vin 1.1 v v ramp current range 2 i ramp en = high 1 100 a en = low, ramp = 19 v ?0.5 +0.5 a pwm comparator pwm comparator offset 2 v osrpm v ramp ? v comp ?3 3 mv rpm comparator rpm current i rpm v vid = 1.2 v, r t = 125 k, varfreq = high see also i rpm (r t ) formula ?8.8 a rpm comparator offset 2 v osrpm v comp ? (1 +v rpm ) ?3 3 mv epwm clock sync trigger threshold 2 relative to comp sampled t clk earlier 2-phase configuration 1-phase configuration 400 450 mv mv switch amplifier sw common mode range 2 v sw(x)cm operating range for current sensing ?600 +200 mv sw resistance r sw_pgnd(x) measured from sw to pgnd 3 k zero current switching comparator sw zcs threshold v dcm(sw1) dcm mode, dprslp = 3.3 v ?6 mv masked off-time t offmskd measured from drvh neg edge to drvh pos edge at max frequency of operation 700 ns system i/o buffers vid[6:0], psi# inputs input voltage refers to driving signal level logic low, i sink 1 a logic high, i source ?5 a 0.7 0.3 v v input current v = 0.2 v vid[6:0], dprslp (active pull down to gnd) psi# (active pull-up to vcc) ?1 +1 a a vid delay time 2 any vid edge to fb change 10% 200 ns dprslp input voltage refers to driving signal level logic low, i sink > 1 a logic high, i source < -5 a 2.3 1.0 v v input current dprslp = low dprslp = high ?1 +2 a a
ADP3208C rev. 1 | page 7 of 41 | www.onsemi.com parameter symbol conditions min typ max units dprstp input voltage refers to driving signal level logic low, i sink 1 a logic high, i source -5 a 0.7 0.3 v v input current 1 a varfreq, sp input voltage refers to driving signal level logic low, i sink 1 a logic high, i source -5 a 4 0.7 v v input current 1 a en input input voltage refers to driving signal level logic low, i sink 1 a logic high, i source -5 a 2.3 1 v v input current en = l or en = h (static) 0.8 v < en < 1.6 v (during transition) 10 70 na a clken output output low voltage logic low, i sink = 4 ma 50 100 mv output high, leakage current logic high, v clken = vcc 1 a thermal monitoring and protection ttsns voltage range 2 0 5 v ttsns threshold vcc = 5 v, ttsns is falling 2.45 2.5 2.55 v ttsns hysteresis 50 110 mv ttsns bias current ttsns = 2.6 v ?2 2 a vrtt output voltage v vrtt logic low, i vrtt(sink) = 400 a logic high, i vrtt(source) = -400 a 4 10 5 100 mv v supply supply voltage range v cc 4.5 5.5 v supply current en = h 6.2 10 ma en = 0 v 15 50 a vcc ok threshold v ccok vcc is rising 4.3 4.5 v vcc uvlo threshold v ccuvlo vcc is falling 4.0 4.1 v vcc hysteresis 2 210 mv high-side mosfet driver pull-up resistance, sourcing current bst = pvcc 1.8 3.3 pull-down resistance, sinking current bst = pvcc 1.0 3 transition times tr drvh, bst = pvcc, c l = 3 nf, figure 2 15 35 ns tf drvh bst = pvcc, c l = 3 nf, figure 2 13 31 ns dead delay times tpdh drvh bst = pvcc, figure 2 39 60 ns bst quiescent current en = l (shutdown) 0.6 5 a en = h, no switching 15 a low-side mosfet driver pull-up resistance, sourcing current 1.6 3.3 pull-down resistance, sinking current 0.8 2.5
ADP3208C rev. 1 | page 8 of 41 | www.onsemi.com parameter symbol conditions min typ max units transition times tr drvl c l = 3 nf, figure 2 15 35 ns tf drvl c l = 3 nf, figure 2 14 35 ns propagation delay times tpdh drvl c l = 3 nf, figure 2 10 30 ns sw transition timeout t tosw drvh = l, sw = 2.5 v 2150 250 450 ns sw off threshold v offsw 1.6 v pvcc quiescent current en = l (shutdown) 1 15 a en = h, no switching 240 a bootstrap rectifier switch on resistance en = l or en = h and drvl = h 3 6 10 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not production tested.
ADP3208C rev. 1 | page 9 of 41 | www.onsemi.com timing diagram timing is referenced to the 90% and 10% points, unless otherwise noted. in drvh (with respect to sw) drvl sw tpdl drvl tf drvl tr drvl tpdl drvh tf drvh tpdh drvh tr drvh v th v th 1v tpdh drvl 06374-006 figure 2. timing diagram
ADP3208C rev. 1 | page 10 of 41 | www.onsemi.com absolute maximum ratings table 2. parameter rating vcc, pvcc1, pvcc2 ?0.3 v to +6 v fbrtn, pgnd1, pgnd2 ?0.3 v to +0.3 v bst1, bst2 dc ?0.3 v to +28 v t < 200 ns ?0.3 v to +33 v bst1 to sw1, bst2 to sw2 ?0.3 v to +6 v sw1, sw2 dc ?5 v to +22 v t < 200 ns ?10 v to +28 v drvh1 to sw1, drvh2 to sw2, ?0.3 v to +6 v drvl1 to pgnd1, drvl2 to pgnd2 dc ?0.3 v to +6 v t < 200 ns ?5 v to +6 v ramp (in shutdown) dc ?0.3 v to +22 v all other inputs and outputs ?0.3 v to +6 v storage temperature ?65c to +150c operating ambient temperature range ?10c to 100c operating junction temperature 125c thermal impedance ( ja ) 2-layer board 40c/w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADP3208C rev. 1 | page 11 of 41 | www.onsemi.com pin configuration and function descriptions 1 ADP3208C (top view) en pwrgd clken fbrtn fb comp ttsns vrtt bst2 drvh2 sw2 drvl2 pgnd2 drvl1 pvcc1 sw1 drvh1 bst1 varfreq nc irpm nc pvcc2 pgnd1 figure 3. lfcsp pin configuration table 3. pin function descriptions pin no. mnemonic description 1 en enable input. driving this pin low shuts down the chip, disables the driver outputs, pulls pwrgd and vrtt low, and pulls clken high. 2 pwrgd power-good output. open-drain output. a low lo gic state means that the output voltage is outside of the vid dac defined range. 3 nc not connected. 4 clken clock enable output. open-drain output. a low lo gic state enables the cpu internal pll clock to lock to the external clock. 5 fbrtn feedback return input/output. th is pin remotely senses the cpu core voltage. it is also used as the ground return for the vid dac and the voltage error amplifier blocks. 6 fb voltage error amplifier feedback input. the inverting input of the voltage error amplifier. 7 comp voltage error amplifier output and frequency compensation point. 8 nc not connected. 9 irpm rpm mode timing control input. a resistor between this pin or rpm pin to ground sets the rpm mode turn-on threshold voltage. if a resistor is connected between this pin to ground, rpm pin must remain floating. 10 varfreq variable frequency enable input. a high logi c state enables the pwm clock frequency to vary with vid code. 11 vrtt voltage regulator thermal throttling output. logic high state indicates that the voltage regulator temperature at the remote sensing point exceeded a set alarm threshold level. 12 ttsns thermal throttling sense and crowbar disable in put. a resistor divider where the upper resistor is connected to vcc, the lower resistor (ntc thermisto r) is connected to gnd, and the center point is connected to this pin and acts as a temperature sensor half bridge. connecting ttsns to gnd disables the thermal throttling function and disables the crowbar, or overvoltage protection (ovp), feature of the chip. 13 imon current monitor output. this pin sources a cu rrent proportional to the output load current. a resistor to fbrtn sets the current monitor gain. 14 rpm rpm mode timing control input. a resistor between this pin or irpm pin to ground sets the rpm mode turn-on threshold voltage. if a resistor is connected between this pin to ground, irpm pin must remain floating. 15 iref this pin sets the internal bi as currents. a 80kohm resistor is connected from this pin to ground.
ADP3208C rev. 1 | page 12 of 41 | www.onsemi.com pin no. mnemonic description 16 lline load line programming input. the center point of a resistor divider connected between csref and cscomp can be tied to this pin to set the load line slope. 17 cscomp current sense amplifier outp ut and frequency compensation point. 18 csref current sense reference input. this pin must be connected to the common point of the output inductors. the node is shorted to gnd through an internal switch when the chip is disabled to provide soft stop transient control of the converter output voltage. 19 cssum current sense summing input. external resist ors from each switch node to this pin sum the inductor currents to provide total current information. 20 ramp pwm ramp slope setting input. an external resi stor from the converter input voltage node to this pin sets the slope of the internal pwm stabil izing ramp used for phase-current balancing. 21 ilimn current limit set. an external resistor from ilimn to ilimp sets the current-limit threshold of the converter. 22 ilimp current limit set. an external resistor from ilimn to ilimp sets the current-limit threshold of the converter. 23 rt pwm oscillator frequency setting input. an exte rnal resistor from this pin to gnd sets the pwm oscillator frequency. 24 gnd analog and digital signal ground. 25 bst2 high-side bootstrap supply for phase 2. a ca pacitor from this pin to sw2 holds the bootstrapped voltage while the high-side mosfet is on. 26 drvh2 high-side gate drive output for phase 2. 27 sw2 current balance input for phase 2 and current return for high-side gate drive. 28 pvcc2 power supply input/output of low-side gate driver for phase 2. 29 drvl2 low-side gate drive output for phase 2. 30 pgnd2 low-side driver power ground for phase 2. 31 pgnd1 low-side driver power ground for phase 1. 32 drvl1 low-side gate drive output for phase 1. 33 pvcc1 power supply input/output of lo w-side gate driver for phase 1. 34 sw1 current balance input for phase 1 and current return for high-side gate drive. 35 drvh1 high-side gate drive output for phase 1. 36 bst1 high-side bootstrap supply for phase 1. a ca pacitor from this pin to sw1 holds the bootstrapped voltage while the high-side mosfet is on. 37 vcc power supply input/output of the controller. 38 sp single-phase select input. logic hi gh state sets single-phase configuration. 39 to 45 vid6 to vid0 voltage identification dac inputs. a 7-bit word (the vid code) programs the dac output voltage, the reference voltage of the voltage error amplifier without a load (see the vid code table, table 6). 46 psi power state indicator input. driving this pin low forces the controller to operate in single-phase mode. 47 dprstp deeper stop control input. the logic state of this pin is usually complementary to the state of the dprslp pin; however, during slow deeper sleep exit, both pins are logic low. 48 dprslp deeper sleep control input.
ADP3208C rev. 1 | page 13 of 41 | www.onsemi.com test circuits vid3 vid2 vid0 psi# dprstp# dprslp vid1 vid6 vid5 vid4 rpm iref lline cscomp csref cssum ramp ilimn imon ilimp sp vcc rt gnd figure 4. closed-loop output voltage accuracy figure 5. current sense amplifier, v os ADP3208C vcc 37 7 6 18 24 comp fb lline gnd + - 1.0v 10k ? 5v csref 16 vid dac v v fb = fb v = v - fb v=0mv figure 6. positioning accuracy
ADP3208C rev. 1 | page 14 of 41 | www.onsemi.com
ADP3208C rev. 1 | page 15 of 41 | www.onsemi.com typical performance characteristics v vid = 1.5 v, t a = 20c to 100c, unless otherwise noted. 50 55 60 65 70 75 80 85 90 9 5 0 5 10 15 20 25 30 35 40 45 l oad current ( a) efficiency (% f = 305 khz sw v = 19 v in v = 9 v in v = 1.2 v out figure 7. pwm mode efficiency vs. load current output voltage sw1 sw2 input = 12v, output = 1v 44a to 9a load step figure 8. load transient with 2 phases output voltage sw1 sw2 input = 12v, output = 1v 9a to 44a load step figure 9. . load transient with 2 phases input = 12v, output = 1.1v no load sw1 sw2 csref to cscomp output ripple figure 10. switching waveforms in 2 phase input = 12v, output = 1.1v no load sw1 sw2 comp output ripple figure 11. switching waveforms in 2 phase
ADP3208C rev. 1 | page 16 of 41 | www.onsemi.com 0 50 100 150 200 250 300 350 400 0.25 0.5 0.75 1 1.25 1.5 v id out put v ol t a ge ( v ) varfreq = 0v varfreq = 5v rt = 187k ? 2 phase mode per phase switching frequency (k hz) figure 12. switching frequency vs. vid output voltage in pwm mode 350 0 01.5 06374-013 output voltage (v) switching frequency (khz) 300 250 200 150 100 50 0.5 1.0 rt = 237k ? rpm = 80.5k ? figure 13. switching frequency vs. output voltage in rpm mode 1200 0 080 06374-014 output power (w) pmon voltage (mv) 1000 800 600 400 200 20 40 60 figure 14. imon voltage vs. output current figure 15. per phase switching frequency vs. rt resistance figure 16. load line accuracy 0 0.2 0.4 0.6 0.8 0123456 vcc voltage (v) vcc current (ma ) vdc = 12v en = low figure 17. vcc current vs. v cc voltage with enable low 100 1000 10 100 1000 rt resistance (k ? ) switching frequency (khz) v id = 0.6125 v id = 0.8125 vid = 1.1v v id = 1.2125v vid = 1.4125v 2 phase configuration 0.85 0.9 0.95 1 1.05 0 1020304050 load (a) output (v) 1 phase psi = low 2 phase psi = high -2% +2%
ADP3208C rev. 1 | page 17 of 41 | www.onsemi.com output v oltag e pwrg d clke n e n figure 18. star t-up waveforms 06374-019 ch1 10.0v ch3 5.00a ref1 10.0v 1.00s ch2 5.00a ch4 20.0mv a ch3 8.00a m1.00s t 20.00% 1 r1 2 4 output voltage l2 current l1 current switch node 1 switch node 2 figure 19. dual-phase, interleaved pwm waveform, 20 a load psi output voltage switch node 1 switch node 2 figure 20. psi transition output voltage switch node 2 switch node 1 figure 21. psi transition dprslp output v olta ge switch node 2 switch node 1 psi = high loa d = 2 a figure 26. dprslp transition psi = high loa d = 2 a switch node 2 output v olta ge switch node 1 dprslp figure 27. dprslp transition
ADP3208C rev. 1 | page 18 of 41 | www.onsemi.com psi = low loa d = 2 a switch node 2 output v olta ge switch node 1 dprslp figure28. dprslp transition psi = low load = 2a switch node 2 output voltage switch node 1 dprslp figure29. dprslp transition
ADP3208C rev. 1 | page 19 of 41 | www.onsemi.com theory of operation the ADP3208C combines multimode pulse-width-modulated (pwm) control and ramp-pulse-modulated (rpm) control with multiphase logic outputs for use in single- and dual-phase synchronous buck cpu core supply power converters. the internal 7-bit vid dac conforms to the intel imvp-6+ specifications. multiphase operation is important for producing the high currents and low voltages demanded by todays microprocessors. handling high currents in a single-phase converter would put too high of a thermal stress on system components such as the inductors and mosfets. the multimode control of the ADP3208C is a stable, high performance architecture that includes ? current and thermal balance between phases ? high speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors ? minimized thermal switching losses due to lower frequency operation ? high accuracy load line regulation ? high current output by supporting 2-phase operation ? reduced output ripple due to multiphase ripple cancellation ? high power conversion efficiency with heavy and light loads ? increased immunity from noise introduced by pc board layout constraints ? ease of use due to independent component selection ? flexibility in design by allowing optimization for either low cost or high performance number of phases the number of operational phases can be set by the user. tying the sp pin to the vcc pin forces the chip into single-phase operation. otherwise, dual-phase operation is automatically selected, and the chip switches between single- and dual-phase modes as the load changes to optimize power conversion efficiency. in dual-phase configuration, sp is low and the timing relationship between the two phases is determined by internal circuitry that monitors the pwm outputs. because each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one output can be active at a time, permitting overlapping phases. operation modes the number of phases can be static (see the number of phases section) or dynamically controlled by system signals to optimize the power conversion efficiency with heavy and light loads. if sp is set low (user-selected dual-phase mode) during a vid transient or with a heavy load condition (indicated by dprslp being low and psi being high), the ADP3208C runs in 2-phase, interleaved pwm mode to achieve minimal v core output voltage ripple and the best transient performance possible. if the load becomes light (indicated by psi being low or dprslp being high), ADP3208C switches to single-phase mode to maximize the power conversion efficiency. in addition to changing the number of phases, the ADP3208C is also capable of dynamically changing the control method. in dual-phase operation, the ADP3208C runs in pwm mode, where the switching frequency is controlled by the master clock. in single-phase operation (commanded by the psi low state), the ADP3208C runs in rpm mode, where the switching frequency is controlled by the ripple voltage appearing on the comp pin. in rpm mode, the drvh1 pin is driven high each time the comp pin voltage rises to a voltage limit set by the vid voltage and an external resistor connected from the rpm to gnd. if the device is in single-phase mode and the system signal dprslp is asserted high during the deeper sleep mode of cpu operation, the ADP3208C continues running in rpm mode but offers the option of turning off the low-side (synchronous rectifier) mosfet when the inductor current drops to 0. turning off the low-side mosfets at the zero current crossing prevents reversed inductor current build up and breaks synchronous operation of high- and low-side switches. due to the asynchronous operation, the switching frequency becomes slower as the load current decreases, resulting in good power conversion efficiency with very light loads. table 4 summarizes how the ADP3208C dynamically changes the number of active phases and transitions the operation mode based on system signals and operating conditions.
ADP3208C rev. 1 | page 20 of 41 | www.onsemi.com table 4. phase number and operation modes 1 psi no. dprslp vid transition 2 current limit no. of phases selected by the user no. of phases in operation operation modes 3 * * yes * n [2 or 1] n pwm, ccm only 1 0 no * n [2 or 1] n pwm, ccm only 0 0 no no * 1 rpm, ccm only 0 0 no yes * 1 pwm, ccm only * 1 no no * 1 rpm, automatic ccm/dcm * 1 no yes * 1 pwm, ccm only 1 * = dont care. 2 vid transient period is the time followin g any vid change, including e ntry into and exit from deeper sleep mode. the duration of vid transient period is the same as that of pwrgd masking time. 3 ccm stands for continuous current mode, and dcm stands for discontinuous current mode. i r = a r i ramp q s rd flip-flop 1v q s rd flip-flop r a c fb r b c a c b vdc v cs r cs c cs r ph r ph drvh drvl gate driver sw vcc l r i l r i load comp fb fbrtn cscomp cssum csref drvl1 sw1 drvh1 c r vrmp bst bst1 5v vcc drvl2 sw2 drvh2 bst2 5v q 400ns q r2 r1 r1 r2 1v 30mv in dcm lline +? + ? + + 0 6 3 7 4 - 0 2 4 figure 22. single-phase rpm mode operation
ADP3208C rev. 1 | page 21 of 41 | www.onsemi.com i r = a r i ramp a d 0.2v clock oscillator q s rd flip-flop i r = a r i ramp a d 0.2v clock oscillator q s rd flip-flop vcc l r i l r i load c r c r drvh drvl gate driver sw vcc drvl1 sw1 drvh1 bst bst1 5v in drvh drvl gate driver sw vcc drvl2 sw2 drvh2 bst bst2 5v ramp r a c fb r b c a c b vdc v cs r cs c cs r ph r ph comp fb fbrtn cscomp cssum csref lline + +? + ? + 0 6 3 7 4 - 0 2 5 figure 23. dual-phase pwm mode operation
ADP3208C rev. 1 | page 22 of 41 | www.onsemi.com setting switch frequency master clock frequency in pwm mode when the ADP3208C runs in pwm, the clock frequency is set by an external resistor connected from the rt pin to gnd. the frequency is constant at a given vid code but varies with the vid voltage: the lower the vid voltage, the lower the clock frequency. the variation of clock frequency with vid voltage maintains constant v core ripple and improves power conversion efficiency at lower vid voltages. figure 15 shows the relationship between clock frequency and vid voltage, parameterized by rt resistance. to determine the switching frequency per phase, divide the clock by the number of phases in use. switching frequency in rpm mode single-phase operation in single-phase rpm mode, the switching frequency is controlled by the ripple voltage on the comp pin, rather than by the master clock. each time the comp pin voltage exceeds the rpm pin voltage threshold level determined by the vid voltage and the external resistor connected from rpm to gnd, an internal ramp signal is started and drvh1 is driven high. the slew rate of the internal ramp is programmed by the current entering the ramp pin. one-third of the ramp current charges an internal ramp capacitor (5 pf typical) and creates a ramp. when the internal ramp signal intercepts the comp voltage, the drvh1 pin is reset low. in continuous current mode, the switching frequency of rpm operation is almost constant. while in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current. differential sensing of output voltage the ADP3208C combines differential sensing with a high accuracy vid dac, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the intel imvp-6+ specification. in steady-state mode, the combination of the vid dac and error amplifier maintain the output voltage for a worst-case scenario within 8 mv of the full operating output voltage and temperature range. the cpu core output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the positive regulation pointthe vcc remote sensing pin of the microprocessor. fbrtn should be connected directly to the negative remote sensing pointthe v ss sensing point of the cpu. the internal vid dac and precision voltage reference are referenced to fbrtn and have a maximum current of 200 a for guaranteed accurate remote sensing. output current sensing the ADP3208C includes a dedicated current sense amplifier (csa) to monitor the total output current of the converter for proper voltage positioning vs. load current and for over current detection. sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low- side mosfet. the current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by ? output inductor esr sensing without the use of a thermistor for the lowest cost ? output inductor esr sensing with the use of a thermistor that tracks inductor temperature to improve accuracy ? discrete resistor sensing for the highest accuracy at the positive input of the csa, the csref pin is connected to the output voltage. at the negative input (that is, the cssum pin of the csa), signals from the sensing element (in the case of inductor dcr sensing, signals from the switch node side of the output inductors) are summed together by series summing resistors. the feedback resistor between the cscomp and cssum pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. the current information is then given as the voltage difference between the cscomp and csref pins. this signal is used internally as a differential input for the current limit comparator. an additional resistor divider connected between the cscomp and csref pins with the midpoint connected to the lline pin can be used to set the load line required by the microprocessor specification. the current information to set the load line is then given as the voltage difference between the lline and csref pins. this configuration allows the load line slope to be set independent from the current limit threshold. if the current limit threshold and load line do not have to be set independently, the resistor divider between the cscomp and csref pins can be omitted and the cscomp pin can be connected directly to lline. to disable voltage positioning entirely (that is, to set no load line), lline should be tied to csref. to provide the best accuracy for current sensing, the csa has a low offset input voltage and the sensing gain is set by an external resistor ratio. active impedance control mode to control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between lline and csref, can be scaled to be equal to the required droop voltage. this droop voltage is calculated by multiplying
ADP3208C rev. 1 | page 23 of 41 | www.onsemi.com the droop impedance of the regulator by the output current. this value is used as the control voltage of the pwm regulator. the droop voltage is subtracted from the dac reference output voltage, and the resulting voltage is used as the voltage positioning setpoint. the arrangement results in an enhanced feedforward response. current control mode and thermal balance the ADP3208C has individual inputs for monitoring the current of each phase. the phase current information is combined with an internal ramp to create a current-balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. the current balance information is independent from the total inductor current information used for voltage positioning described in the active impedance control mode section. the magnitude of the internal ramp can be set so that the transient response of the system is optimal. the ADP3208C monitors the supply voltage to achieve feedforward control whenever the supply voltage changes. a resistor connected from the power input voltage rail to the ramp pin determines the slope of the internal pwm ramp. more detail about programming the ramp is provided in the application information section. the ADP3208C should not require external thermal balance circuitry if a good layout is used. however, if mismatch is desired due to uneven cooling in phase, external resistors can be added to individually control phase currents as long as the phase currents are mismatched by less than 30%. if unwanted mismatch exceeds 30%, a new layout that improves phase symmetry should be considered. figure 24. optional current balance resistors in 2-phase operation, alternate cycles of the internal ramp control the duty cycle of the separate phases. figure 24 shows the addition of two resistors from each switch node to the ramp pin; this modifies the ramp-charging current individually for each phase. during phase 1, sw node 1 is high (practically at the input voltage potential) and sw node 2 is low (practically at the ground potential). as a consequence, the ramp pin, through the r2 resistor, sees the tap point of a divider connected to the input voltage, where r sw1 is the upper element and r sw2 is the lower element of the divider. during phase 2, the voltages on sw node 1 and sw node 2 switch and the resistors swap functions. tuning r sw1 and r sw2 allows the current to be optimally set for each phase. to increase the current for a given phase, decrease r sw for that phase. voltage control mode a high-gain bandwidth error amplifier is used for the voltage mode control loop. the noninverting input voltage is set via the 7-bit vid dac. the vid codes are listed in table 6. the noninverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. the output of the error amplifier is the comp pin, which sets the termination voltage of the internal pwm ramps. at the negative input, the fb pin is tied to the output sense location using r b , a resistor for sensing and controlling the output voltage at the remote sensing point. the main loop compensation is incorporated in the feedback network connected between the fb and comp pins. power-good monitoring the power-good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output that can be pulled up through an external resistor to a voltage rail not necessarily the same vcc voltage rail that is running the controller. a logic high level indicates that the output voltage is within the voltage limits defined by a range around the vid voltage setting. pwrgd goes low when the output voltage is outside of this range. following the imvp-6+ specification, the pwrgd range is defined to be 300 mv less than and 200 mv greater than the actual vid dac output voltage. for any dac voltage less than 300 mv, only the upper limit of the pwrgd range is monitored. to prevent a false alarm, the power-good circuit is masked during various system transitions, including a vid change and entrance into or exit out of deeper sleep. the duration of the pwrgd mask is set to approximately 130 s by an internal timer. if the voltage drop is greater than 200 mv during deeper sleep entry or slow deeper sleep exit, the duration of pwrgd masking is extended by the internal logic circuit. power-up sequence and soft start the power-on ramp-up time of the output voltage is set internally. the power-up sequence, including the soft start is illustrated in figure 25. after en is asserted high, the soft start sequence starts. the core voltage ramps up linearly to the boot voltage. the ADP3208C regulates at the boot voltage for 100 s. after the boot time is completed, clken# is asserted low. after clken# is asserted low for 9ms, pwrgd is asserted high.
ADP3208C rev. 1 | page 24 of 41 | www.onsemi.com in vcc uvlo or in shutdown, a small mosfet turns on connecting the csref to gnd. the mosfet on the csref pin has a resistance of approximately 100. when vcc ramps above the upper uvlo threshold and en is asserted high, the ADP3208C enables internal bias and starts a reset cycle that lasts about 50 s to 60 s. next, when initial reset is over, the chip detects the number of phases set by the user, and gives a go signal to start soft start. the ADP3208C reads the vid codes provided by the cpu on vid0 to vid6 input pins after clken# is asserted low.the pwrgd signal is asserted after a t cpu_pwrgd delay of about 9 ms, as specified by imvp-6+. the power-good delay is programmed internally. figure 25. power-up sequence of ADP3208C if en is taken low or vcc drops below the vcc uvlo threshold, both the ss capacitor and the pgdelay capacitor are reset to ground to prepare the chip for a subsequent soft start cycle. soft transient when a vid input changes, the ADP3208C detects the change but ignores new code for a minimum of 400 ns. this delay is required to prevent the device from reacting to digital signal skew while the 7- bit vid input code is in transition. additionally, the vid change triggers a pwrgd masking timer to prevent a pwrgd failure. each vid change resets and retriggers the internal pwrgd masking timer. the ADP3208C provides a soft transient function to reduce inrush current during vid transitions. reducing the inrush current helps decrease the acoustic noise generated by the mlcc input capacitors and inductors. the soft transient feature is implemented internally. when a new vid code is detected, the ADP3208C steps sequentially through each vid voltage to the final vid voltage. there is a pwrgd masking time of 100s after the last vid code is changed internally. table 5 lists the soft transient slew rate. table 5. soft transient slew rate vid transient dprslp slew rate entrance to deeper sleep high ?3.125mv/s fast exit from deeper sleep low +12.5mv/s slow exit from deeper sleep high +3.125mv/s transient from v boot to vid dnc 1 3.125mv/s current limit the ADP3208C compares the differential output of a current- sense amplifier to a programmable current-limit setpoint to provide current-limiting function. the current limit set point is set with a resistor connected from ilim pin to cscomp pin. this is the r lim resistor. during normal operation, the voltage on the ilim pin is equal to the csref pin. the voltage across r lim is equal to the voltage across the current sense amplifier (from csref pin to cscomp pin). this voltage is proportional to output current. the current through r lim is proportional to the output inductor current. the current through r lim is compared with an internal reference current. when the r lim current goes above the internal reference current, the ADP3208C goes into current limit. the current limit circuit is shown in figure 28. figure28. current limit circuit during start-up when the output voltage is below 200 mv, a secondary current limit is activated. this is necessary because the voltage swing on cscomp cannot extend below ground. the secondary current-limit circuit clamps the internal comp voltage and sets the internal compensation ramp termination voltage at 1.5 v level. the clamp actually limits voltage drop across the low side mosfets through the current balance circuitry. an inherent per phase current limit protects individual phases in case one or more phases stop functioning because of a faulty component. this limit is based on the maximum normal-mode comp voltage.
ADP3208C rev. 1 | page 25 of 41 | www.onsemi.com after 9ms in current limit, the adp3207c will latch off . the latch-off can be reset by removing and reapplying vcc, or by recycling the en pin low and high for a short time. the latch-off can be reset by removing and reapplying vcc, or by recycling the en pin low and high for a short time. pwrgd 2v/div output 0.5v/div 2ms/div current limit applied latched off figure 26. current overload changing vid on the fly the ADP3208C is designed to track dynamically changing vid code. as a consequence, the cpu vcc voltage can change without the need to reset the controller or the cpu. this concept is com- monly referred to as vid on-the-fly (vid otf) transient. a vid otf can occur with either light or heavy load conditions. the processor alerts the controller that a vid change is occurring by changing the vid inputs in lsb incremental steps from the start code to the finish code. the change can be either upwards or downwards steps. when a vid input changes, the ADP3208C detects the change but ignores new code for a minimum of 400 ns. this delay is required to prevent the device from reacting to digital signal skew while the 7-bit vid input code is in transition. additionally, the vid change triggers a pwrgd masking timer to prevent a pwrgd failure. each vid change resets and retriggers the internal pwrgd masking timer. as listed in table 6, during a vid transient, the ADP3208C forces pwm mode regardless of the state of the system input signals. for example, this means that if the chip is configured as a dual-phase controller but is running in single-phase mode due to a light load condition, a current overload event causes the chip to switch to dual-phase mode to share the excessive load until the delayed current limit latch-off cycle terminates. in user-set single-phase mode, the ADP3208C usually runs in rpm mode. when a vid transition occurs, however, the ADP3208C switches to dual-phase pwm mode. light load rpm dcm operation in single-phase normal mode, dprslp is pulled low and the apd3208 operates in continuous conduction mode (ccm) over the entire load range. the upper and lower mosfets run synchronously and in complementary phase. see figure 27 for the typical waveforms of the ADP3208C running in ccm with a 7 a load current. 06374-030 3 1 2 4 400ns/div output voltage 20mv/div inductor current 5a/div switch node 5v/div low-side gate drive 5v/div figure 27. single-phase waveforms in ccm if dprslp is pulled high, the ADP3208C operates in rpm mode. if the load condition is light, the chip enters discontinuous conduction mode (dcm). figure 28 shows a typical single-phase buck with one upper fet, one lower fet, an output inductor, an output capacitor, and a load resistor. figure 29 shows the path of the inductor current with the upper fet on and the lower fet off. in figure 30 the high-side fet is off and the low-side fet is on. in ccm, if one fet is on, its complementary fet must be off; however, in dcm, both high- and low-side fets are off and no current flows into the inductor (see figure 31). figure 32 shows the inductor current and switch node voltage in dcm. in dcm with a light load, the ADP3208C monitors the switch node voltage to determine when to turn off the low-side fet. figure 33 shows a typical waveform in dcm with a 1 a load current. between t 1 and t 2 , the inductor current ramps down. the current flows through the source drain of the low-side fet and creates a voltage drop across the fet with a slightly negative switch node. as the inductor current ramps down to 0 a, the switch voltage approaches 0 v, as seen just before t 2 . when the switch voltage is approximately ?6 mv, the low-side fet is turned off. figure 32 shows a small, dampened ringing at t 2 . this is caused by the lc created from capacitance on the switch node, including the c ds of the fets and the output inductor. this ringing is normal. the ADP3208C automatically goes into dcm with a light load. figure 33 shows the typical dcm waveform of the ADP3208C. as the load increases, the ADP3208C enters into ccm. in dcm, frequency decreases with load current. figure 34 shows switching frequency vs. load current for a typical design. in dcm, switching frequency is a function of the inductor, load current, input voltage, and output voltage.
ADP3208C rev. 1 | page 26 of 41 | www.onsemi.com switch node l drvl drvh q1 q2 c output voltage load input v oltage 06374-031 figure 28. buck topology l c on off load 06374-032 figure 29. buck topology inductor current during t 0 and t 1 l c on off load 06374-033 figure 30. buck topology inductor current during t 1 and t 2 l c off off load 06374-034 figure 31. buck topology inductor current during t 2 and t 3 inductor current switch node voltage t 0 t 1 t 2 t 3 t 4 06374-035 figure 32. inductor current and switch node in dcm 06374-036 3 1 2 4 2s/div switch node 5v/div low-side gate drive 5v/div output voltage 20mv/div inductor current 5a/div figure 33. single-phase waveform s in dcm with 1 a load current 400 0 014 06374-037 load current (a) frequency (khz) 350 300 250 200 150 100 50 2 4 6 8 10 12 19v input 9v input figure 34. single-phase ccm/dcm frequency vs. load current output crowbar to prevent the cpu and other external components from damage due to overvoltage, the ADP3208C turns off the drvh1 and drvh2 outputs and turns on the drvl1 and drvl2 outputs when the output voltage exceeds the ovp threshold (1.7 v typical). turning on the low-side mosfets forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. if the output overvoltage is due to a drain- source short of the high-side mosfet, turning on the low-side mosfet results in a crowbar across the input voltage rail. the crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the microprocessor from destruction. when the ovp feature is triggered, the ADP3208C is latched off. the latch-off function can be reset by removing and reapplying vcc to the ADP3208C or by briefly pulling the en pin low.
ADP3208C rev. 1 | page 27 of 41 | www.onsemi.com pulling ttsns to less than 1 v disables the overvoltage protection function. in this configuration, vrtt should be tied to ground. reverse voltage protection very large reverse current in inductors can cause negative v core voltage, which is harmful to the cpu and other output components. the ADP3208C provides a reverse voltage protection (rvp) function without additional system cost. the v core voltage is monitored through the csref pin. when the csref pin voltage drops to less than ?300 mv, the ADP3208C triggers the rvp function by disabling all pwm outputs and driving drvl1 and drvl2 low, thus turning off all mosfets. the reverse inductor currents can be quickly reset to 0 by discharging the built-up energy in the inductor into the input dc voltage source via the forward-biased body diode of the high-side mosfets. the rvp function is terminated when the csref pin voltage returns to greater than ?100 mv. sometimes the crowbar feature inadvertently causes output reverse voltage because turning on the low-side mosfets results in a very large reverse inductor current. to prevent damage to the cpu caused from negative voltage, the ADP3208C maintains its rvp monitoring function even after ovp latch-off. during ovp latch-off, if the csref pin voltage drops to less than ?300 mv, the low-side mosfets is turned off. drvl outputs are allowed to turn back on when the csref voltage recovers to greater than ?100 mv. figure 37 shows a typical over voltage protection test. fb pin is shorted to ground causing the control to command a large duty cycle. the output voltage climbs up. when the output voltage is climbs 200 mv above the dac voltage, the pwrgd signal de-asserts. when the output voltage climbs to 1.7v, over voltage protection is enabled. in over voltage protection, the phase 1 and phase 2 low side drive turns on the low side power mosfets. the low side mosfets pull the output voltage low through the power inductor. when the output voltage falls below -300 mv, reverse voltage protection is enabled. in reverse voltage protection, all power mosfets are turned off. this protects the cpu from seeing a large negative voltage. output voltage pwrgd phase 2 low side gate phase 1 low side gate figure 37. over voltage protection and reverse voltage protection output enable and uvlo for the ADP3208C to begin switching, the vcc supply voltage to the controller must be greater than the v ccok threshold and the en pin must be driven high. if the vcc voltage is less than the v ccuvlo threshold or the en pin is a logic low, the ADP3208C shuts off. in shutdown mode, the controller holds the pwm outputs low, shorts the capacitors of the ss and pgdelay pins to ground, and drives the drvh and drvl outputs low. the user must adhere to proper power-supply sequencing during startup and shutdown of the ADP3208C. all input pins must be at ground prior to removing or applying vcc, and all output pins should be left in high impedance state while vcc is off. thermal throttling control the ADP3208C includes a thermal monitoring circuit to detect whether the temperature of the vr has exceeded a user-defined thermal throttling threshold. the thermal monitoring circuit requires an external resistor divider connected between the vcc pin and gnd. the divider consists of an ntc thermistor and a resistor. to generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the ttsns pin. an internal comparator circuit compares the ttsns voltage to half the vcc threshold and outputs a logic level signal at the vrtt output when the temperature trips the user-set alarm threshold. the vrtt output is designed to drive an external transistor that in turn provides the high current, open-drain vrtt signal required by the imvp-6+ specification. the internal vrtt comparator has a hysteresis of approximately 100 mv to prevent high frequency oscillation of vrtt when the temperature approaches the set alarm point. current monitor function the ADP3208C has an output current monitor. the imon pin sources a current proportional to the inductor current. a resistor from imon pin to fbrtn sets the gain. a 0.1 f is
ADP3208C rev. 1 | page 28 of 41 | www.onsemi.com added in parallel with r mon to filter the inductor ripple. the imon pin is clamped to prevent it from going above 1.15v
ADP3208C rev. 1 | page 29 of 41 | www.onsemi.com table 6. vid codes vid6 vid5 vid4 vid3 vi d2 vid1 vid0 output 0 0 0 0 0 0 0 1.5000 v 0 0 0 0 0 0 1 1.4875 v 0 0 0 0 0 1 0 1.4750 v 0 0 0 0 0 1 1 1.4625 v 0 0 0 0 1 0 0 1.4500 v 0 0 0 0 1 0 1 1.4375 v 0 0 0 0 1 1 0 1.4250 v 0 0 0 0 1 1 1 1.4125 v 0 0 0 1 0 0 0 1.4000 v 0 0 0 1 0 0 1 1.3875 v 0 0 0 1 0 1 0 1.3750 v 0 0 0 1 0 1 1 1.3625 v 0 0 0 1 1 0 0 1.3500 v 0 0 0 1 1 0 1 1.3375 v 0 0 0 1 1 1 0 1.3250 v 0 0 0 1 1 1 1 1.3125 v 0 0 1 0 0 0 0 1.3000 v 0 0 1 0 0 0 1 1.2875 v 0 0 1 0 0 1 0 1.2750 v 0 0 1 0 0 1 1 1.2625 v 0 0 1 0 1 0 0 1.2500 v 0 0 1 0 1 0 1 1.2375 v 0 0 1 0 1 1 0 1.2250 v 0 0 1 0 1 1 1 1.2125 v 0 0 1 1 0 0 0 1.2000 v 0 0 1 1 0 0 1 1.1875 v 0 0 1 1 0 1 0 1.1750 v 0 0 1 1 0 1 1 1.1625 v 0 0 1 1 1 0 0 1.1500 v 0 0 1 1 1 0 1 1.1375 v 0 0 1 1 1 1 0 1.1250 v 0 0 1 1 1 1 1 1.1125 v 0 1 0 0 0 0 0 1.1000 v 0 1 0 0 0 0 1 1.0875 v 0 1 0 0 0 1 0 1.0750 v 0 1 0 0 0 1 1 1.0625 v 0 1 0 0 1 0 0 1.0500 v 0 1 0 0 1 0 1 1.0375 v 0 1 0 0 1 1 0 1.0250 v 0 1 0 0 1 1 1 1.0125 v 0 1 0 1 0 0 0 1.0000 v 0 1 0 1 0 0 1 0.9875 v 0 1 0 1 0 1 0 0.9750 v 0 1 0 1 0 1 1 0.9625 v 0 1 0 1 1 0 0 0.9500 v 0 1 0 1 1 0 1 0.9375 v 0 1 0 1 1 1 0 0.9250 v 0 1 0 1 1 1 1 0.9125 v 0 1 1 0 0 0 0 0.9000 v 0 1 1 0 0 0 1 0.8875 v 0 1 1 0 0 1 0 0.8750 v 0 1 1 0 0 1 1 0.8625 v 0 1 1 0 1 0 0 0.8500 v 0 1 1 0 1 0 1 0.8375 v 0 1 1 0 1 1 0 0.8250 v 0 1 1 0 1 1 1 0.8125 v 0 1 1 1 0 0 0 0.8000 v 0 1 1 1 0 0 1 0.7875 v 0 1 1 1 0 1 0 0.7750 v 0 1 1 1 0 1 1 0.7625 v 0 1 1 1 1 0 0 0.7500 v 0 1 1 1 1 0 1 0.7375 v 0 1 1 1 1 1 0 0.7250 v 0 1 1 1 1 1 1 0.7125 v vid6 vid5 vid4 vid3 vi d2 vid1 vid0 output 1 0 0 0 0 0 0 0.7000 v 1 0 0 0 0 0 1 0.6875 v 1 0 0 0 0 1 0 0.6750 v 1 0 0 0 0 1 1 0.6625 v 1 0 0 0 1 0 0 0.6500 v 1 0 0 0 1 0 1 0.6375 v 1 0 0 0 1 1 0 0.6250 v 1 0 0 0 1 1 1 0.6125 v 1 0 0 1 0 0 0 0.6000 v 1 0 0 1 0 0 1 0.5875 v 1 0 0 1 0 1 0 0.5750 v 1 0 0 1 0 1 1 0.5625 v 1 0 0 1 1 0 0 0.5500 v 1 0 0 1 1 0 1 0.5375 v 1 0 0 1 1 1 0 0.5250 v 1 0 0 1 1 1 1 0.5125 v 1 0 1 0 0 0 0 0.5000 v 1 0 1 0 0 0 1 0.4875 v 1 0 1 0 0 1 0 0.4750 v 1 0 1 0 0 1 1 0.4625 v 1 0 1 0 1 0 0 0.4500 v 1 0 1 0 1 0 1 0.4375 v 1 0 1 0 1 1 0 0.4250 v 1 0 1 0 1 1 1 0.4125 v 1 0 1 1 0 0 0 0.4000 v 1 0 1 1 0 0 1 0.3875 v 1 0 1 1 0 1 0 0.3750 v 1 0 1 1 0 1 1 0.3625 v 1 0 1 1 1 0 0 0.3500 v 1 0 1 1 1 0 1 0.3375 v 1 0 1 1 1 1 0 0.3250 v 1 0 1 1 1 1 1 0.3125 v 1 1 0 0 0 0 0 0.3000 v 1 1 0 0 0 0 1 0.2875 v 1 1 0 0 0 1 0 0.2750 v 1 1 0 0 0 1 1 0.2625 v 1 1 0 0 1 0 0 0.2500 v 1 1 0 0 1 0 1 0.2375 v 1 1 0 0 1 1 0 0.2250 v 1 1 0 0 1 1 1 0.2125 v 1 1 0 1 0 0 0 0.2000 v 1 1 0 1 0 0 1 0.1875 v 1 1 0 1 0 1 0 0.1750 v 1 1 0 1 0 1 1 0.1625 v 1 1 0 1 1 0 0 0.1500 v 1 1 0 1 1 0 1 0.1375 v 1 1 0 1 1 1 0 0.1250 v 1 1 0 1 1 1 1 0.1125 v 1 1 1 0 0 0 0 0.1000 v 1 1 1 0 0 0 1 0.0875 v 1 1 1 0 0 1 0 0.0750 v 1 1 1 0 0 1 1 0.0625 v 1 1 1 0 1 0 0 0.0500 v 1 1 1 0 1 0 1 0.0375 v 1 1 1 0 1 1 0 0.0250 v 1 1 1 0 1 1 1 0.0125 v 1 1 1 1 0 0 0 0.0000 v 1 1 1 1 0 0 1 0.0000 v 1 1 1 1 0 1 0 0.0000 v 1 1 1 1 0 1 1 0.0000 v 1 1 1 1 1 0 0 0.0000 v 1 1 1 1 1 0 1 0.0000 v 1 1 1 1 1 1 0 0.0000 v 1 1 1 1 1 1 1 0.0000 v
ADP3208C rev. 1 | page 30 of 41 | www.onsemi.com figure 35. typical dual-phase application circuit
ADP3208C rev. 1 | page 31 of 41 | www.onsemi.com application information the design parameters for a typical imvp-6+-compliant cpu core vr application are as follows: ? maximum input voltage (v inmax ) = 19 v ? minimum input voltage (v inmin ) = 8 v ? output voltage by vid setting (v vid ) = 1.4375 v ? maximum output current (i o ) = 40 a ? droop resistance (r o ) = 2.1 m ? nominal output voltage at 40 a load (v ofl ) = 1.3535 v ? static output voltage drop from no load to full load (v) = v onl ? v ofl = 1.4375 v ? 1.3535 v = 84 mv ? maximum output current step (i o ) = 27.9 a ? number of phases (n) = 2 ? switching frequency per phase (f sw ) = 300 khz ? duty cycle at maximum input voltage (d max ) = 0.18 v ? duty cycle at minimum input voltage (d min ) = 0.076 v setting the clock frequency for pwm in pwm operation, the ADP3208C uses a fixed-frequency control architecture. the frequency is set by an external timing resistor (rt). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. for a dual-phase design, a clock frequency of 600 khz sets the switching frequency to 300 khz per phase. this selection represents the trade-off between the switching losses and the minimum sizes of the output filter components. to achieve a 600 khz oscillator frequency at a vid voltage of 1.2 v, rt must be 187 k. alternatively, the value for rt can be calculated by using the following equation: ? + = k pf f n v v r sw vid t 16 9 2 1 (1) where: 9 pf and 16 k are internal ic component values. v vid is the vid voltage in volts. n is the number of phases. f sw is the switching frequency in hertz for each phase. for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. when varfreq pin is connected to ground, the switching frequency does not change with vid. the value for rt can be calculated by using the following equation. ? = k pf f n v r sw t 16 9 1 (2) for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. setting the switching frequency for rpm operation of phase 1 during the rpm mode operation of phase 1, the ADP3208C runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. while in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. when considering power conversion efficiency in light load, lower switching frequency is usually preferred for rpm mode. however, the v core ripple specification in the imvp-6 sets the limitation for lowest switching frequency. therefore, depending on the inductor and output capacitors, the switching frequency in rpm mode can be equal, larger, or smaller than its counterpart in pwm mode. a resistor from rpm to gnd sets the pseudo constant frequency as following: ? ? + = k 5 . 0 ) 1 ( v 0 . 1 2 sw r r vid r vid t rpm f c r v d a v r r (24) where: a r is the internal ramp amplifier gain. c r is the internal ramp capacitor value. r r is an external resistor on the rampadj pin to set the internal ramp magnitude. because r r = 280 k, the following resistance sets up 300 khz switching frequency in rpm operation. ? k 202 500 khz 300 pf 5 ? k 462 150 . 1 ) 061 . 0 1 ( 5 . 0 v 0 . 1 v 150 . 1 ? k 280 2 = ? ? + = rpm r inductor selection the choice of inductance determines the ripple current of the inductor. less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the mosfets. however, this allows the use of smaller-size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. for a multiphase converter, the practical value for peak-to-peak inductor ripple current is less than 50% of the maximum dc current of that inductor. equation 3 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple
ADP3208C rev. 1 | page 32 of 41 | www.onsemi.com current. equation 4 can be used to determine the minimum inductance based on a given output ripple voltage. l f d v i sw min vid r ? = ) 1 ( (3) ripple sw min o vid v f d n r v l ? )) ( 1 ( (4) solving equation 4 for a 16 mv peak-to-peak output ripple voltage yields () nh 533 mv 16 khz 0 0 3 076 . 0 2 1 m ? 1 . 2 v 75 3 4 1. = ? l if the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. this iteration allows optimal transient response and minimum output decoupling. the smallest possible inductor should be used to minimize the number of output capacitors. choosing a 490 nh inductor is a good choice for a starting point, and it provides a calculated ripple current of 9.0 a. the inductor should not saturate at the peak current of 24.5 a, and it should be able to handle the sum of the power dissipation caused by the windings average current (20 a) plus the ac core loss. in this example, 330 nh is used. another important factor in the inductor design is the dcr, which is used for measuring the phase currents. too large of a dcr causes excessive power losses, whereas too small of a value leads to increased measurement error. for this example, an inductor with a dcr of 0.8 m is used. selecting a standard inductor after the inductance and dcr are known, select a standard inductor that best meets the overall design goals. it is also important to specify the inductance and dcr tolerance to maintain the accuracy of the system. using 20% tolerance for the inductance and 15% for the dcr at room temperature are reasonable values that most manufacturers can meet. power inductor manufacturers the following companies provide surface-mount power inductors optimized for high power applications upon request: ? vishay dale electronics, inc. (605) 665-9301 ? panasonic (714) 373-7334 ? sumida electric company (847) 545-6700 ? nec tokin corporation (510) 324-4110 output droop resistance the design requires that the regulator output voltage measured at the cpu pins decreases when the output current increases. the specified voltage drop corresponds to the droop resistance (r o ). the output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. the summing is implemented by the cs amplifier that is configured with resistor r ph(x) (summer) and resistors r cs and c cs (filters). the output resistance of the regulator is set by the following equations: sense x ph cs o r r r r = ) ( (5) cs sense cs r r l c = (6) where r sense is the dcr of the output inductors. either r cs or r ph(x) can be chosen for added flexibility. due to the current drive ability of the cscomp pin, the r cs resistance should be greater than 100 k. for example, initially select r cs to be equal to 200 k, and then use equation 6 to solve for c cs : nf 1 . 2 k 200 m 8 . 0 nh 330 = = cs c if c cs is not a standard capacitance, r cs can be tuned. for example, if the optimal c cs capacitance is 1.5 nf, adjust r cs to 280 k. for best accuracy, c cs should be a 5% npo capacitor. in this example, a 220 k is used for r cs to achieve optimal results. next, solve for r ph(x) by rearranging equation 5 as follows: k 8 . 83 k 220 m 1 . 2 m 8 . 0 ) ( = x ph r the standard 1% resistor for r ph(x) is 86.6 k. inductor dcr temperature correction if the dcr of the inductor is used as a sense element and copper wire is the source of the dcr, the temperature changes associated with the inductors winding must be compensated for. fortunately, copper has a well-known temperature coefficient (tc) of 0.39%/c. if r cs is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductors dcr. due to the nonlinear nature of ntc thermistors, series resistors r cs1 and r cs2 (see figure 36) are needed to linearize the ntc and produce the desired temperature coefficient tracking.
ADP3208C rev. 1 | page 33 of 41 | www.onsemi.com figure 36. temperature-compensation circuit values the following procedure and expressions yield values for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value. 1. select an ntc to be used based on its type and value. because the value needed is not yet determined, start with a thermistor with a value close to r cs and an ntc with an initial tolerance of better than 5%. 2. find the relative resistance value of the ntc at two temperatures. the appropriate temperatures will depend on the type of ntc, but 50c and 90c have been shown to work well for most types of ntcs. the resistance values are called a (a is r th (50c)/r th (25c)) and b (b is r th (90c)/r th (25c)). note that the relative value of the ntc is always 1 at 25c. 3. find the relative value of r cs required for each of the two temperatures. the relative value of r cs is based on the percentage of change needed, which is initially assumed to be 0.39%/c in this example. the relative values are called r 1 (r 1 is 1/(1+ tc ( t 1 ? 25))) and r 2 (r 2 is 1/(1 + tc ( t 2 ? 25))), where tc is 0.0039, t 1 is 50c, and t 2 is 90c. 4. compute the relative values for r cs1 , r cs2 , and r th by using the following equations: ) ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) ( b a r a b r b a r a b r b a r r b a r 2 1 1 2 2 1 cs2 ? ? ? ? ? ? + ? ? ? = (7) cs2 1 cs2 cs1 r r a r a r ? ? ? ? = 1 1 ) 1 ( cs1 cs2 th r r r 1 1 1 1 ? ? = 5. calculate r th = r th r cs , and then select a thermistor of the closest value available. in addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: ) ( ) ( calculated th actual th r r k = (8) 6. calculate values for r cs1 and r cs2 by using the following equations: cs1 cs cs1 r k r r = (9) )) ( ) 1 (( cs2 cs cs2 r k k r r + ? = for example, if a thermistor value of 100 k is selected in step 1, an available 0603-size thermistor with a value close to r cs is the vishay nths0603n04 ntc thermistor, which has resistance values of a = 0.3359 and b = 0.0771. using the equations in step 4, r cs1 is 0.359, r cs2 is 0.729, and r th is 1.094. solving for r th yields 241 k, so a thermistor of 220 k would be a reasonable selection, making k equal to 0.913. finally, r cs1 and r cs2 are found to be 72.1 k and 166 k. choosing the closest 1% resistor for r cs2 yields 165 k. to correct for this approximation, 73.3 k is used for r cs1 . c out selection the required output decoupling for processors and platforms is typically recommended by intel. for systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. select the number of ceramics and determine the total ceramic capacitance (c z ). this is based on the number and type of capacitors used. keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805-size pieces inside the socket. additional ceramic capacitors can be placed along the outer edge of the socket. a combined ceramic capacitor value of 200 f to 300 f is recommended and is usually composed of multiple 10 f or 22 f capacitors. ensure that the total amount of bulk capacitance (c x ) is within its limits. the upper limit is dependent on the vid on-the-fly output voltage stepping (voltage step, v v , in time, t v , with error of v err ); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, i o . the current version of the imvp-6+ specification allows a maximum v core overshoot (v osmax ) of 10 mv more than the vid voltage for a step-off load current. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + z vid o osmax o o min x c v i v r n i l c (10) z o v vid v vid v o max x c l r k n v v t v v r k n l c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 2 2 ) ( where ? ? ? ? ? ? ? ? ? = v err v v k ln (11)
ADP3208C rev. 1 | page 34 of 41 | www.onsemi.com to meet the conditions of these expressions and the transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is greater than c x(max) , the system does not meet the vid on-the-fly and/or the deeper sleep exit specifications and may require less inductance or more phases. in addition, the switching frequency may have to be increased to maintain the output ripple. for example, if 30 pieces of 10 f, 0805-size mlc capacitors (c z = 300 f) are used, the fastest vid voltage change is when the device exits deeper sleep, during which the v core change is 220 mv in 22 s with a setting error of 10 mv. if k = 3.1, solving for the bulk capacitance yields () mf 0 . 1 f 300 v 4375 . 1 a 9 . 27 mv 10 m 1 . 2 2 a 9 . 27 nh 330 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + min x c () v 4375 . 1 ) m 1 . 2 ( 1 . 3 2 mv 220 nh 330 2 2 max x c f 300 1 nh 0 49 mv 0 22 m 1 . 2 1 . 3 2 v 75 3 4 1. s 2 2 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 21 mf using six 330 f panasonic sp capacitors with a typical esr of 7 m each yields c x = 1.98 mf and r x = 1.2 m. ensure that the esl of the bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using 2 2 q r c l o z x (12) () nh 2 2 m 1 . 2 f 300 2 = x l where: q is limited to the square root of 2 to ensure a critically damped system. l x is about 150 ph for the six sp capacitors, which is low enough to avoid ringing during a load change. if the l x of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. for this multimode control technique, an all ceramic capacitor design can be used if the conditions of equations 10, 11, and 12 are satisfied. power mosfets for typical 20 a per phase applications, the n-channel power mosfets are selected for two high-side switches and two or three low-side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . because the voltage of the gate driver is 5 v, logic- level threshold mosfets must be used. the maximum output current, i o , determines the r ds(on) requirement for the low-side (synchronous) mosfets. in the ADP3208C, currents are balanced between phases; the current in each low-side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and the average total output current (i o ): ) ( 2 2 12 1 ) 1 ( sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = (13) where: d is the duty cycle and is approximately the output voltage divided by the input voltage. i r is the inductor peak-to-peak ripple current and is approximately sw out r f l v d i ? = ) 1 ( knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required r ds(on) for the mosfet. for 8-lead soic or 8-lead soic- compatible mosfets, the junction-to-ambient (pcb) thermal impedance is 50c/w. in the worst case, the pcb temperature is 70c to 80c during heavy load operation of the notebook, and a safe limit for p sf is about 0.8 w to 1.0 w at 120c junction tem- perature. therefore, for this example (40 a maximum), the r ds(sf) per mosfet is less than 8.5 m for two pieces of low-side mosfets. this r ds(sf) is also at a junction temperature of about 120c; therefore, the r ds(sf) per mosfet should be less than 6 m at room temperature, or 8.5 m at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous mosfets when the switch node goes high. the high-side (main) mosfet must be able to handle two main power dissipation components: conduction losses and switching losses. switching loss is related to the time for the main mosfet to turn on and off and to the current and voltage that are being switched. basing the switching speed on the rise and fall times of the gate driver impedance and mosfet input capacitance, the following expression provides an approximate value for the switching loss per main mosfet:
ADP3208C rev. 1 | page 35 of 41 | www.onsemi.com iss mf g m f o dc sw mf s c n n r n i v f p = 2 ) ( (14) where: n mf is the total number of main mosfets. r g is the total gate resistance. c iss is the input capacitance of the main mosfet. the most effective way to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the following equation: ) ( 2 2 ) ( 12 1 mf ds mf r mf o mf c r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = (15) where r ds(mf) is the on resistance of the mosfet. typically, a user wants the highest speed (low c iss ) device for a main mosfet, but such a device usually has higher on resistance. therefore, the user must select a device that meets the total power dissipation (about 0.8 w to 1.0 w for an 8-lead soic) when combining the switching and conduction losses. for example, an irf7821 device can be selected as the main mosfet (four in total; that is, n mf = 4), with approximately c iss = 1010 pf (maximum) and r ds(mf) = 18 m (maximum at t j = 120c), and an ir7832 device can be selected as the synchronous mosfet (four in total; that is, n sf = 4), with r ds(sf) = 6.7 m (maximum at t j = 120c). solving for the power dissipation per mosfet at i o = 40 a and i r = 9.0 a yields 630 mw for each synchronous mosfet and 590 mw for each main mosfet. a third synchronous mosfet is an option to further increase the conversion efficiency and reduce thermal stress. finally, consider the power dissipation in the driver for each phase. this is best described in terms of the q g for the mosfets and is given by the following equation: () vcc i q n q n n f p cc gsf sf gmf mf sw drv ? ? ? ? ? ? + + = 2 (16) where q gmf is the total gate charge for each main mosfet, and q gsf is the total gate charge for each synchronous mosfet. the previous equation also shows the standby dissipation (i cc times the vcc) of the driver. ramp resistor selection the ramp resistor (r r ) is used to set the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. use the following expression to determine a starting value: (17) = = = k 462 pf 5 m 2 . 5 5 3 nh 360 5 . 0 3 r r ds d r r r c r a l a r where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low-side mosfet on-resistance, c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 18). for stability and noise immunity, keep the ramp size larger than 0.5 v. taking this into consideration, the value of r r in this example is selected as 280 k. the internal ramp voltage magnitude can be calculated as follows: v 83 . 0 khz 280 pf 5 k 462 v 150 . 1 ) 061 . 0 1 ( 5 . 0 ) 1 ( = ? = ? = r sw r r vid r r v f c r v d a v (18) the size of the internal ramp can be increased or decreased. if it is increased, stability and transient response improves but thermal balance degrades. conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. in the denominator of equation 17, the factor of 3 sets the minimum ramp size that produces an optimal combination of good stability, transient response, and thermal balance. comp pin ramp in addition to the internal ramp, there is a ramp signal on the comp pin due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input: () ? ? ? ? ? ? ? ? ? ? = o x sw r rt r c f n d n v v 1 2 1 (19) where c x is the total bulk capacitance, and r o is the droop resistance of the regulator. for this example, the overall ramp signal is 1.85 v.
ADP3208C rev. 1 | page 36 of 41 | www.onsemi.com current limit setpoint to select the current-limit setpoint, we need to find the resistor value for r lim . the current-limit threshold for the ADP3208C is set when the current in r lim is equal to the internal reference current of 20 a. the current in r lim is equal to the inductor current times r o . r lim can be found using the following equation: a r i r o lim lim 20 = (25) where: r lim is the current limit resistor. r lim is connected from the ilim pin to ground. r o is the output load line resistance. i lim is the current limit set point. this is the peak inductor current that will trip current limit. in this example, if choosing 55 a for i lim , r lim is 5.775 k, which is close to a standard 1% resistance of 5.76 k. the per-phase current limit described earlier has its limit determined by the following: 2 ) ( ) ( r max ds d bias r max comp phlim i r a v v v i + ? ? ? (26) for the ADP3208C, the maximum comp voltage (v comp(max) ) is 3.3 v, the comp pin bias voltage (v bias ) is 1.0 v, and the current balancing amplifier gain (a d ) is 5. using a v r of 0.55 v, and a r ds(max) of 3.8 m (low-side on-resistance at 150c) results in a per-phase limit of 85 a. although this number seems high, this current level can only be reached with a absolute short at the output and the current-limit latch-off function shutting down the regulator before overheating occurs. this limit can be adjusted by changing the ramp voltage v r . however, users should not set the per-phase limit lower than the average per-phase current (i lim /n). there is also a per-phase initial duty-cycle limit at maximum input voltage: r bias max comp min lim v v v d d ? = ) ( (27) for this example, the duty-cycle limit at maximum input voltage is found to be 0.25 when d is 0.061. output current monitor the ADP3208C has output current monitor. the imon pin sources a current proportional to the total inductor current. a resistor, r mon , from imon to fbrtn sets the gain of the output current monitor. a 0.1 f is placed in parallel with r mon to filter the inductor current ripple and high frequency load transients. since the imon pin is connected directly to the cpu, it is clamped to prevent it from going above 1.15v. the imon pin current is equal to the r lim times a fixed gain of 10. r mon can be found using the following equation: fs o lim mon i r r v r = 10 15 . 1 (28) where: r mon is the current monitor resistor. r mon is connected from imon pin to fbrtn. r lim is the current limit resistor. r o is the output load line resistance. i fs is the output current when the voltage on imon is at full scale. feedback loop compensation design optimized compensation of the ADP3208C allows the best possible response of the regulators output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. with the multimode feedback structure of the ADP3208C, it is necessary to set the feedback compensation so that the converters output impedance works in parallel with the output decoupling. in addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). a type iii compensator on the voltage feedback is adequate for proper compensation of the output filter. figure 37 shows the type iii amplifier used in the ADP3208C. figure 38 shows the locations of the two poles and two zeros created by this amplifier.
ADP3208C rev. 1 | page 37 of 41 | www.onsemi.com r a c b r fb c a c fb comp fb reference voltage voltage error amplifier ADP3208C output voltage figure 37. voltage error amplifier gain 0db frequency f p1 f z2 f p2 f z1 ?20db/dec ?20db/dec 06374-043 figure 38. poles and zeros of voltage error amplifier the following equations give the locations of the poles and zeros shown in figure 38: a a z1 r c f = 2 1 (20) fb fb z2 r c f = 2 1 (21) fb b a p1 r c c f + = ) ( 2 1 (22) a b a b a p2 c c r c c f + = 2 (23) the expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning procedure for ADP3208C section): + + + = vid rt l ds d o e v v r r a r n r (24) vid o x rt v r c n v d n l ? )) ( 1 ( 2 () x o o x o x a r r r r l r r c t ' ' ? + ? = (25) ( ) x o x b c r r r t ? + = ' (26) e vid sw ds d rt c r v f r a l v t ? ? ? ? ? ? ? ? ? = 2 (27) () o z o x o z x d r c r r c r c c t + ? = ' 2 (28) where: r ' is the pcb resistance from the bulk capacitors to the ceramics and is approximately 0.4 m (assuming an 8-layer motherboard). r ds is the total low-side mosfet for on resistance per phase. a d is 5. v rt is 1.25 v. l x is 150 ph for the six panasonic sp capacitors. the compensation values can be calculated as follows: b e a o a r r t r n c = (29) a c a c t r = (30) b b b r t c = (31) a d fb r t c = (32) the standard values for these components are subject to the tuning procedure described in the tuning procedure for ADP3208C section. c in selection and input current di/dt reduction in continuous inductor-current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out / v in and an amplitude that is one-n th of the maximum output current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the maximum rms capacitor current occurs at the lowest input voltage and is given by 1 1 ? = d n i d i o crms (33) a 6 . 9 1 0.18 2 1 a 40 18 . 0 = ? = crms i where i o is the output current. in a typical notebook system, the battery rail decoupling is achieved by using mlc capacitors or a mixture of mlc capacitors and bulk capacitors. in this example, the input
ADP3208C rev. 1 | page 38 of 41 | www.onsemi.com capacitor bank is formed by eight pieces of 10 f, 25 v mlc capacitors, with a ripple current rating of about 1.5 a each. selecting thermal monitor components to monitor the temperature of a single-point hot spot, set r ttset1 equal to the ntc thermistors resistance at the alarm temperature. for example, if the alarm temperature for vrtt is 100c and a vishey thermistor (nths-0603n011003j) with a resistance of 100 k at 25c, or 6.8 k at 100c, is used, the user can set r ttset1 equal to 6.8 k (the r th1 at 100c). figure 39. single-point thermal monitoring to monitor the temperature of multiple-point hot spots, use the configuration shown in figure 40. if any of the monitored hot spots reaches the alarm temperature, the vrtt signal is asserted. the following calculation sets the alarm temperature: mperature th1alarmte ref fd ref fd ttset1 r v v v v r ? + = 2 / 1 2 / 1 (34) where v fd is the forward drop voltage of the parallel diode. because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mv. assuming the same conditions used for the single-point thermal monitoring examplethat is, an alarm temperature of 100c and use of an nths-0603n011003j vishay thermistorsolving equation 42 gives a r ttset of 7.37 k, and the closest standard resistor is 7.32 k (1%). figure 40. multiple-point thermal monitoring the number of hot spots monitored is not limited. the alarm temperature of each hot spot can be individually set by using different values for r ttset1 , r ttset2 , r ttsetn . tuning procedure for ADP3208C set up and test the circuit 1. build a circuit based on the compensation values computed from the design spreadsheet. 2. connect a dc load to the circuit. 3. turn on the ADP3208C and verify that it operates properly. 4. check for jitter with no load and full load conditions. set the dc load line 1. measure the output voltage with no load (v nl ) and verify that this voltage is within the specified tolerance range. 2. measure the output voltage with a full load when the device is cold (v flcold ). allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (v flhot ). if the difference between the two measured voltages is more than a few millivolts, adjust r cs2 using equation 35. flhot nl flcold nl cs2(old) cs2(new) v v v v r r ? ? = (35) 3. repeat step 2 until no adjustment of r cs2 is needed. 4. compare the output voltage with no load to that with a full load using 5 a steps. compute the load line slope for each change and then find the average to determine the overall load line slope (r omeas ). 5. if the difference between r omeas and r o is more than 0.05 m, use the following equation to adjust the r ph values: o omeas old ph new ph r r r r = ) ( ) ( (36) 6. repeat steps 4 and 5 until no adjustment of r ph is needed. once this is achieved, do not change r ph , r cs1 , r cs2 , or r th for the rest of the procedure. 7. measure the output ripple with no load and with a full load with scope, making sure both are within the specifications. set the ac load line 1. remove the dc load from the circuit and connect a dynamic load. 2. connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 s/div. 3. set the dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 4. measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). try to use a vertical scale of 100 mv/div or finer.
ADP3208C rev. 1 | page 39 of 41 | www.onsemi.com 5. the resulting waveform will be similar to that shown in figure 41. use the horizontal cursors to measure v acdrp and v dcdrp , as shown in figure 41. do not measure the under- shoot or overshoot that occurs immediately after the step. v dcdrp v acdrp 06374-046 figure 41. ac load line waveform 6. if the difference between v acdrp and v dcdrp is more than a couple of millivolts, use equation 46 to adjust c cs . it may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason). dcdrp acdrp old cs new cs v v c c = ) ( ) ( (37) 7. repeat steps 5 and 6 until no adjustment of c cs is needed. once this is achieved, do not change c cs for the rest of the procedure. 8. set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning v acdrp and v dcdrp are equal. 9. ensure that the load step slew rate and the power-up slew rate are set to ~150 a/s to 250 a/s (for example, a load step of 50 a should take 200 ns to 300 ns) with no overshoot. some dynamic loads have an excessive overshoot at power-up if a minimum current is incorrectly set (this is an issue if a vtt tool is in use). set the initial transient 1. with the dynamic load set at its maximum step size, expand the scope time scale to 2 s/div to 5 s/div. this results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after v droop (see figure 42). v droop v tran2 v tran1 06374-047 figure 42. transient setting waveform, load step 2. if both overshoots are larger than desired, try the following adjustments in the order shown. a. increase the resistance of the ramp resistor (r ramp ) by 25%. b. for v tran1 , increase c b or increase the switching frequency. c. for v tran2 , increase r a by 25% and decrease c a by 25%. if these adjustments do not change the response, it is because the system is limited by the output decoupling. check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. for load release (see figure 43), if v tranrel is larger than the value specified by imvp-6+, a greater percentage of output capacitance is needed. either increase the capacitance directly or decrease the inductor values. (if inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures). v droop v tranrel 06374-048 figure 43. transient setting waveform, load release layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system.
ADP3208C rev. 1 | page 40 of 41 | www.onsemi.com general recommendations 1. for best results, use a pcb of four or more layers. this should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. 2. when high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. if critical signal lines (including the output voltage sense lines of the ADP3208C) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. an analog ground plane should be used around and under the ADP3208C for referencing the components associated with the controller. this plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. 5. the components around the ADP3208C should be located close to the controller with short traces. the most important traces to keep short and away from other traces are those to the fb and cssum pins. refer to figure 36 for more details on the layout for the cssum node. 6. the output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). if the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. 7. avoid crossing signal lines over the switching power path loop, as described in the power circuitry section. power circuitry 1. the switching power path on the pcb should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-related operational problems in the power-converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. the use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 2. when a power-dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the pcb, where a plane can more readily transfer heat to the surrounding air. to achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the mosfets on the opposite side of the pcb. in addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. for best emi containment, a solid power ground plane should be used as one of the inner layers and extended under all power components. signal circuitry 1. the output voltage is sensed and regulated between the fb and fbrtn pins, and the traces of these pins should be connected to the signal ground of the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. therefore, the fb and fbrtn traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be kelvin connected to the center point of the copper bar, which is the v core common node for the inductors of all the phases. 3. on the back of the ADP3208C package, there is a metal pad that can be used to heat sink the device. therefore, running vias under the ADP3208C is not recommended because the metal pad may cause shorting between vias.
ADP3208C rev. 1 | page 41 of 41 | www.onsemi.com outline dimension pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 44. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option package marking ordering quantity ADP3208Cjcpz-rl 1 -10c to 100c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 line 1: ADP3208C line 2: awlyywg 2,500 1 z = rohs compliant part. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scil lc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal op portunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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